Rosa M. Badia holds a PhD on Computer Science (1994) from the Technical University of Catalonia (UPC). She is the manager of the Workflows and Distributed Computing research group at the Barcelona Supercomputing Center (BSC). She is considered one of the key researchers in Parallel programming models for multicore and distributed computing due to her contribution to task-based programming models during the last 15 years. The research group focuses on PyCOMPSs/COMPSs, a parallel task-based programming distributed computing, and its application to the development of large heterogeneous workflows that combine HPC, Big Data, and Machine Learning. The group is also doing research around the dislib, a parallel machine learning libray parallelized with PyCOMPSs. Dr Badia has published near 200 papers in international conferences and journals on the topics of her research. She has been very active in projects funded by the European Commission in contracts with industry. She has been actively contributing to the BDEC international initiative and is a member of HiPEAC Network of Excellence. She received the Euro-Par Achievement Award 2019 for her contributions to parallel processing and the DonaTIC award, category Academia/Researcher in 2019. She is the IP of the EuroHPC project eFlows4HPC.
Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. He has been visiting professor at Stanford University, IMEC, EPFL. He served as chief architect in STmicroelectronics France. Dr. Benini's research interests are in energy-efficient parallel computing systems, smart sensing micro-systems and machine learning hardware. He has published more than 1000 peer-reviewed papers and five books (h-index 110). He is an ERC-advanced grant winner, a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award, the EDAA Achievement and the ACM/IEEE A. Richard Newton awards in 2020.
Josep Lluís Berral received his Engineering degree in Informatics (2007), M.Sc. in Computer Architecture (2008), and Ph.D. in Computer Science (2013) at BarcelonaTech-UPC. He works in High-Performance Data-Analytics on data-center and cloud environments at the Barcelona Supercomputing Center (BSC), at the “Data-Centric Computing” group. He is currently collaborating in projects with IBM, Intel, Databricks and Petrobras, and previously with Microsoft and Cisco. He did research at the High-Performance Computing group and at the Relational Algorithms, Complexity and Learning group at BarcelonaTech-UPC. Also he has been at the DarkLab group at Rutgers University (Piscataway, NJ) as a Visitor Scholar in 2012, also in IBM Watson Labs (Yorktown, NY) in 2019. He was awarded with a Juan de la Cierva research fellowship from the Spanish Ministry of Economy in 2016. He is an IEEE and ACM member.
Luca Cardelli has an M.Sc. in computer science from the University of Pisa, and a Ph.D. in computer science from the University of Edinburgh. He worked at Bell Labs, Murray Hill, from 1982 to 1985, and at Digital Equipment Corporation, Systems Research Center in Palo Alto, from 1985 to 1997, and at Microsoft Research, in Cambridge UK from 1997 to 2018 where he was head of the Programming Principles and Tools and Security groups until 2012. Since 2013 he has been a Royal Society Research Professor at the University of Oxford. His main interests are in programming languages and concurrency, and more recently in programmable biology and nanotechnology. He is a Fellow of the Royal Society, a Fellow of the Association for Computing Machinery, an Elected Member of the Academia Europaea, and an Elected Member of the Association Internationale pour les Technologies Objets.
Marc Casas is a senior researcher at the Barcelona Supercomputing Center (BSC). His research focuses on the analysis and simulation of high-performance computing systems, on developing efficient mathematical libraries for scientific computing, and on improving computer architectures and parallel systems via accurate prediction methodologies. He is the main creator of the MUltiscale-Simulation Approach (MUSA), a simulation and analysis tool for large-scale systems and applications. He supervises a group of PhD students, engineers, and postdocs. Marc leads BSC's contribution to the Mont-Blanc2020 project and research collaborations with Intel and IBM. Marc has been at BSC since 2013. He was a postdoctoral research scholar at the Lawrence Livermore National Laboratory (LLNL) from 2010 to 2013. He received the Marie Curie and Ramón y Cajal Fellowships on 2014 and 2018, respectively. He obtained a 5-years degree in mathematics in 2004, and a PhD degree in Computer Science in 2010 from the Universitat Politècnica de Catalunya (UPC).
Sunita Chandrasekaran is an Associate Professor with the Department of Computer and Information Sciences at the University of Delaware, USA. She received her Ph.D. in 2012 on Tools and Algorithms for High-Level Algorithm Mapping to FPGAs from the School of Computer Science and Engineering, Nanyang Technological University, Singapore. Her research spans High Performance Computing, interdisciplinary science, machine learning and data science. She is a recipient of the 2016 IEEE-CS TCHPC Award for Excellence for Early Career Researchers in High Performance Computing. Chandrasekaran has been involved in the technical program and organization committees of several conferences and workshops including SC, ISC, IPDPS, IEEE Cluster, CCGrid, WACCPD, AsHES and P3MA.
Bio to come.
Dr. John D. Davis is the Director of the Laboratory for Open Computer Architecture at Barcelona Supercomputing Center. He has published over 30 refereed conference and journal papers in Computer Architecture (ASIC and FPGA-based domain-specific accelerators, non-volatile memories and processor design), Distributed Systems, and Bioinformatics. He also holds over 35 issued or pending patents in the USA and Europe. He has designed and built distributed storage systems in research and as products. John has led the entire product strategy, roadmap, and execution for a big data and analytics company. He has worked in research at Microsoft Research, where he also co-advised 4 PhDs, as well as large and small start-up companies. John holds a B.S. in Computer Science and Engineering from the University of Washington. He also holds a M.S. and Ph.D. in Electrical Engineering from Stanford University. At BSC, John is leading the MEEP project and is the technical leader of the eProcesor project and the European PILOT project. He also leads several industrial research collaborations, all centered around a full open source ecosystem from software down to hardware, open source processors and accelerators. John is the founder and chair of the RISC-V Special Interest Group on High Performance Computing (SIG-HPC).
Roger Espasa got his Phd in Computer Science from Universitat Politècnica de Catalunya in 1997. Between 1999 and 2001 he worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture known as Tarantula. Between 2002 and 2014 Roger worked at Intel developing a vector extension for the x86 ISA which was initially deployed in the Larrabee and Knight's Corner product and then became the AVX-512 extension. Roger also led the team implementing the texture sampling unit for the original Larrabee chip. Roger also worked on the core for the Knight's Landing product (14nm) and led the core for the follow-on Knights Hill 10nm product. In 2014, Roger joined Broadcom where he worked on a from-scratch ARMV8 wide out-of-order core supporting both A64 and A32.In 2016 Roger founded SemiDynamics Technology Services where he is working on RISC-V cores. Among other things, SemiDynamics architected and designed the 1024+ core machine learning 7nm SoC for Esperanto Technologies. Currently SemiDynamics is providing two RISC-V IP Cores, Avispado (in-order) and Atrevido (out-of-order) that support the RISC-V vector extension. Roger has published over 40 peer-reviewed papers on Vector Architectures, Graphics/3D Architecture, Binary translation and optimization, Branch Prediction, and Media ISA Extensions. Roger holds 9 patents with 41 international filings.
Prof. Jesús Labarta received his Ph.D. in Telecommunications Engineering from UPC in 1983, where he has been a full professor of Computer Architecture since 1990. He was Director of European Center of Parallelism at Barcelona from 1996 to the creation of BSC in 2005, where he is the Director of the Computer Sciences Dept. His research team has developed performance analysis and prediction tools and pioneering research on how to increase the intelligence embedded in these performance tools. He has also led the development of OmpSs and influenced the task based extension in the OpenMP standard. He has led the BSC cooperation with many IT companies. He is now responsible of the POP center of excellence providing performance assessments to parallel code developers throughout the EU and leads the RISC-V vector accelerator within the EPI project. He has pioneered the use of Artificial Intelligence in performance tools and will promote their use in POP, as well as the AI-centric co-designing of architectures and runtime systems. He was awarded the 2017 Ken Kennedy Award for his seminal contributions to programming models and performance analysis tools for high performance computing, being the First Non US Researcher receiving it.
Mauro Olivieri received the Master (Laurea) degree in electronics engineering and the Doctorate degree in electronics and computer engineering from the University of Genoa, Italy, where he was assistant professor from 1995 to 1998. In 1998 he joined Sapienza University of Rome as associate professor, teaching Digital Electronics and Digital Integrated System Architectures. His research interests are digital system-on-chip design, microprocessor core design and digital nano-scale circuits. He was the scientific responsible for Sapienza University for 2 FP7 ENIAC JU European projects, 1 FP7 IAPP European project, 4 PRIN/FIRB national projects, 11 MIUR University Projects, and 8 industrial research contracts. He was a technical expert for the Italian Economic Development Ministry in the “Smart Specialization Strategy” project on the topic “Smart Cities/Communities”. He is an evaluator for the European Commission in the ECSEL Joint Undertaking. He is a visiting researcher at the Barcelona Supercomputing Center within the European Processor Initiative project. He authored over 120 papers and a textbook in three volumes on digital VLSI design. He has been a TPC member of IEEE DATE and was General Co-Chair of IEEE/ACM ISLPED’15. He is a senior member of the IEEE.
Mihaela van der Schaar is the John Humphrey Plummer Professor of Machine Learning, Artificial Intelligence and Medicine at the University of Cambridge, a Fellow at The Alan Turing Institute in London, and a Chancellor’s Professor at UCLA. Mihaela’s research focus is on machine learning, AI and operations research for healthcare and medicine. In addition to leading the van der Schaar Lab, Mihaela is founder and director of the Cambridge Centre for AI in Medicine (CCAIM).
Mihaela was elected IEEE Fellow in 2009. She has received numerous awards, including the Oon Prize on Preventative Medicine from the University of Cambridge (2018), a National Science Foundation CAREER Award (2004), 3 IBM Faculty Awards, the IBM Exploratory Stream Analytics Innovation Award, the Philips Make a Difference Award and several best paper awards, including the IEEE Darlington Award. Mihaela’s work has also led to 35 USA patents (many widely cited and adopted in standards) and 45+ contributions to international standards for which she received 3 International ISO (International Organization for Standardization) Awards. In 2019, she was identified by National Endowment for Science, Technology and the Arts as the most-cited female AI researcher in the UK. She was also elected as a 2019 “Star in Computer Networking and Communications” by N²Women. Her research expertise spans signal and image processing, communication networks, network science, multimedia, game theory, distributed systems, machine learning and AI.
I’m a Professor at the Universitat Politècnica de Catalunya UPC Barcelona Tech and, Research Manager of the research group “Emerging Technologies for Artificial Intelligence” at Barcelona Supercomputing Center. Throughout my career, I have applied High-Performance Computing knowledge to areas like Cloud Computing or Big Data. My current research focuses on Supercomputing applied to Deep Learning and Reinforcement Learning. I have taught academic subjects in all these areas, wrote scientific publications, advised doctoral theses and, participated in R&D projects with companies and institutions. I’m also a writer of technical books, and in the past, I collaborated actively with different mass media and gave lectures in various forums.
Director of the Barcelona Supercomputing Center. His research focuses on high performance architectures. He has published approximately 700 papers, has served in the organization of more than 300 International Conferences and he has given more than 500 invited talks. Prof. Valero has been honored with several awards, among them the 3 most relevant awards in Computer Architecture field: the Eckert-Mauchly Award 2007 by the IEEE and ACM; Seymour Cray Award 2015 by IEEE; Charles Babbage 2017 by IEEE; Harry Goode Award 2009 by IEEE:; the Spanish National awards “Julio Rey Pastor” and “Leonardo Torres Quevedo”. "Hall of the Fame" member of the ICT European Program (selected as one of the 25 most influents European researchers in IT during the period 1983-2008. Lyon,November 2008); In 2020 he has been awarded for his exceptional leadership in HPC by “HPCWire Reader’s Choice Awards” for “being an HPC pioneer since 1990 and the driving force behind the renaissance of European HPC independence”. Honored with “Condecoración de la Orden Mexicana del Águila Azteca” 2018, highest recognition granted by the Mexican Government. He is Honorary Doctorate by 9 Universities. He is member of 9 academies. He is a fellow of IEEE and ACM and he is also Intel Distinguished Research Fellow. In 1998 he won a “Favourite Son” Award of his home town, Alfamén (Zaragoza) and in 2006, his native town of Alfamén named their Public College after him.
Uri Weiser is a Professor emeritus at the Electrical and Computing Engineering (ECE) department, the Technion IIT and is involved in numerous startups. He received his bachelor and master degrees in EE from the Technion and Ph.D in CS from the University of Utah, Salt Lake City. Professor Weiser worked at Intel corporation from 1988-2006. At Intel, Weiser initiated the definition of the Pentium® processor, drove the definition of Intel's MMX™ technology, invented the Trace Cache, co-managed the new Intel Microprocessor Design Center at Austin, Texas and formed an Advanced Media applications research activity. Weiser was appointed an Intel Fellow in 1996. In 2002 he became an IEEE Fellow and in 2005 an ACM Fellow, while in 2016 he was awarded the prestigious Eckert Mauchly award. Prior to his career at Intel, Professor Weiser worked for the Israeli Department of Defense as a research and system engineer and later with National Semiconductor Design Center in Israel, where he led the design of the NS32532 microprocessor.