Rosa Badia holds a PhD on Computer Science (1994) from the Technical University of Catalonia (UPC). She is the manager of the Workflows and Distributed Computing research group at the Barcelona Supercomputing Center (BSC). Her current research interest are programming models for complex platforms (from edge, fog, to Clouds and large HPC systems). The group led by Dr. Badia has been developing StarSs programming model for more than 10 years, with a high success in adoption by application developers. Currently the group focuses its efforts in PyCOMPSs/COMPSs, an instance of the programming model for distributed computing including Cloud. Dr Badia has published near 200 papers in international conferences and journals in the topics of her research. Her group is very active in projects funded by the European Commission and in contracts with industry. Dr Badia is the PI of the eFlows4HPC project.
Andrea Bartolini holds an assistant professor (RTD-B) position with the Department of Electrical, Electronic and Information Engineering (Guglielmo Marconi) at the University of Bologna. He was a postdoctoral researcher with Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich. He has authored or co-authored more than 135 papers in peer-reviewed international journals and conferences, and several book chapters with focus on dynamic resource management—ranging from embedded to large scale HPC systems. He has collaborated with several international research and companies. Andrea Bartolini has been the main responsible for the design of advanced power management and monitoring support on the first Cavium ThunderX cluster, the D.A.V.I.D.E. and Marconi100 supercomputers. Since 2018 Andrea Bartolini serves as the technical leader for the European-processor-initiative power management design. In 2021, Andrea Bartolini collaborated with CINECA and E4 engineering in the design of the Monte Cimone HPC cluster – the first RISC-V HPC cluster.
Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. Dr. Benini’s research interests are in energy-efficient parallel computing systems, smart sensing micro-systems and machine learning hardware. He is a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award, the 2020 EDAA achievement Award, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS E.J. McCluskey Award.
Josep Lluís Berral received his Engineering degree in Informatics (2007), M.Sc. in Computer Architecture (2008), and Ph.D. in Computer Science (2013) at BarcelonaTech-UPC. He works in High-Performance Data-Analytics on data-center and cloud environments in the "Computing Resources Orchestration and Management" group at Universitat Politècnica de Catalunya (UPC), and in the "Data-Centric Computing" group at the Barcelona Supercomputing Center (BSC). He is currently collaborating in projects with IBM and Petrobras, and previously with Microsoft, Intel, Databricks and Cisco. He did research at the High-Performance Computing group and at the Relational Algorithms, Complexity and Learning group atBarcelonaTech-UPC. Also he has been at the DarkLab group at Rutgers University (Piscataway, NJ) as a Visitor Scholar in 2012, also in IBM Watson Labs (Yorktown, NY) in 2019. He was awarded with a Juan de la Cierva research fellowship from the Spanish Ministry of Economy in 2016, and the Advanced Research recognition I3 in 2023. He is an IEEE and ACM member.
Alba Cervera-Lierta is a Senior Researcher at the Barcelona Supercomputing Center. She earned her PhD in 2019 at the University of Barcelona, where she studied her physics degree and a Msc in particle physics. After her PhD, she moved to the University of Toronto as a postdoctoral fellow at the Alán Aspuru-Guizik group. She works on near-term quantum algorithms and their applications, high-dimensional quantum computation, and artificial intelligence strategies in quantum physics. Since October of 2021, she is the coordinator of the Quantum Spain project, an initiative to boost the quantum computing ecosystem that will install and operate a quantum computer at the BSC-CNS.
Jorge Ejarque holds PhD on Computer Science (2015) from the Technical University of Catalonia (UPC). From 2005 to 2008 he worked as research support engineer at the UPC, and joined Barcelona Supercomputing Center BSC at the end of 2008 in the Workflows and Distributed Computing Team. He has contributed in the design and development of different tools and programming models for managing complex workflows in distributed computing platforms. He has published over 30 research papers in conferences and journals and he has been involved in several National and European R&D projects (FP6, FP7, H2020 and Horizon Europe). He is member of a program committee of several international conferences, reviewer of journal articles and he was member of the Spanish National Grid Initiative panel. His current research interests are focused on parallel programming models for heterogeneous parallel distributed computing environments and the interoperability between distributed computing platforms.
Mario Kovač is full professor at the Faculty of Electrical Engineering and Computing (FER), University of Zagreb, Croatia and Director of HPC Architectures and Applications Research Center at FER. He received his PhD in computer science and engineering from the same university in 1995. He was awarded Fulbright scholar award for Computer Science and Engineering Research that he spent at the University of South Florida, Tampa, USA between 1990 and 1994. His special focus was on efficient chip implementation of architectures for image, video and math computation processing that led to several chips including Jaguar chip. He holds several US and international patents in multimedia and architecture domains. His work on architectures and efficient execution was focused over time in several industry domains: multimedia systems, large national/cross-national health-care systems, electric cars and other. In 2008, Croatian President awarded him with the Medal of Honor "Order of Danica Hrvatska with the image of Ruđer Bošković" for special merit in science. His professional activities throughout years were always intertwined combination of science and industry activities. He was President/Vice-president of the Board and CxO of several organisations and companies where he was primarily involved in strategic management and R&D.
Prof. Jesús Labarta received his Ph.D. in Telecommunications Engineering from UPC in 1983, where he has been a full professor of Computer Architecture since 1990. He was Director of European Center of Parallelism at Barcelona from 1996 to the creation of BSC in 2005, where he is the Director of the Computer Sciences Dept. His research team has developed performance analysis and prediction tools and pioneering research on how to increase the intelligence embedded in these performance tools. He has also led the development of OmpSs and influenced the task based extension in the OpenMP standard. He has led the BSC cooperation with many IT companies. He is now responsible of the POP center of excellence providing performance assessments to parallel code developers throughout the EU and leads the RISC-V vector accelerator within the EPI project. He has pioneered the use of Artificial Intelligence in performance tools and will promote their use in POP, as well as the AI-centric co-designing of architectures and runtime systems. He was awarded the 2017 Ken Kennedy Award for his seminal contributions to programming models and performance analysis tools for high performance computing, being the First Non US Researcher receiving it.
Dr. Lamport's research has been centered on concurrency and fault-tolerance. He is the inventor of several well-known concurrent and distributed algorithms, including early algorithms for tolerating "Byzantine" faults. He has also developed methods for formally specifying and verifying concurrent systems. Dr. Lamport has received six honorary doctorates, the PODC Influential Paper Award, two Dijkstra Prizes in Distributed Computing, three ACM SIGOPS Hall of Fame Awards, two Jean-Claude Laprie Awards in Dependable Computing, the IEEE Piore Award, the IEEE John von Neumann Medal, and the ACM Turing award. He has been elected to the U.S. National Academy of Sciences, the U.S. National Academy of Engineering, and the American Academy of Arts and Sciences.
Mauro Olivieri received the Master (Laurea) degree in electronics engineering and the Doctorate degree in electronics and computer engineering from the University of Genoa, Italy, where he was assistant professor from 1995 to 1998. In 1998 he joined Sapienza University of Rome as associate professor, teaching Digital Electronics and Digital Integrated System Architectures. His research interests are digital system-on-chip design, microprocessor core design and digital nano-scale circuits. He was the scientific responsible for Sapienza University for 2 FP7 ENIAC JU European projects, 1 FP7 IAPP European project, 4 PRIN/FIRB national projects, 11 MIUR University Projects, and 8 industrial research contracts. He was a technical expert for the Italian Economic Development Ministry in the “Smart Specialization Strategy” project on the topic “Smart Cities/Communities”. He is an evaluator for the European Commission in the ECSEL Joint Undertaking. He is a visiting researcher at the Barcelona Supercomputing Center within the European Processor Initiative project. He authored over 120 papers and a textbook in three volumes on digital VLSI design. He has been a TPC member of IEEE DATE and was General Co-Chair of IEEE/ACM ISLPED’15. He is a senior member of the IEEE.
Per Stenström is professor at Chalmers University of Technology. His research interests are in parallel computer architecture. He has authored or co-authored four textbooks, about 200 publications and twenty patents in this area. He has been program chairman of several top-tier IEEE and ACM conferences including IEEE/ACM Symposium on Computer Architecture and acts as Associate Editor of ACM TACO, Topical Editor IEEE Transaction on Computers and Associate Editor-in-Chief of JPDC. He is a Fellow of the ACM and the IEEE and a member of Academia Europaea, the Royal Swedish Academy of Engineering Sciences and the Royal Spanish Academy of Engineering Science.
Mateo Valero, http://www.bsc.es/cv-mateo/" is profesor of Computer Architecture at Technical University of Catalonia (UPC) and is the Founding Director of the Barcelona Supercomputing Center, where his research focuses on high performance computing architectures. He has published approximately 700 papers, has served in the organization of more than 300 International Conferences and has given more than 600 invited talks. Prof. Valero has been honored with numerous awards, among them: The Eckert-Mauchly Award 2007 by IEEE and ACM, the Seymour Cray Award 2015 by IEEE and the Charles Babbage 2017 by IEEE. Among other awards, Prof. Valero has received The Harry Goode Award 2009 by IEEE, The Distinguish Service Award by ACM and the Spanish National awards “Julio Rey Pastor” and “Leonardo Torres Quevedo”. Prof. Valero is a "Hall of the Fame" member of the ICT European Program (selected as one of the 25 most influents European researchers in IT during the period 1983-2008, Lyon, November 2008). In 2020 he was awarded the “HPCWire Reader’s Choice Awards” “for his exceptional leadership in HPC” and for “being an HPC pioneer since 1990 and the driving force behind the renaissance of European HPC independence”. He has been also honored with “Condecoración de la Orden Mexicana del Águila Azteca” 2018, the highest recognition granted by the Mexican Government. Prof. Valero holds Honorary Doctorate by 10 Universities, is member of 10 academies and a fellow of IEEE and ACM, and Fellow of AAIA, Asia-Pacific Artificial Intelligence Association. In 1998 Mateo Valero was distinguished as “Favourite Son” of his home town, Alfamén (Zaragoza) and in 2006, his native town of Alfamén named its Public School after him.
Uri Weiser is a Professor emeritus at the Electrical and Computing Engineering (ECE) department, the Technion IIT and is involved in numerous startups. He received his bachelor and master degrees in EE from the Technion and Ph.D in CS from the University of Utah, Salt Lake City. Professor Weiser worked at Intel corporation from 1988-2006. At Intel, Weiser initiated the definition of the first Pentium® processor, drove the definition of Intel's MMX™ technology, with his student invented the Trace Cache, co-managed the founding Intel Microprocessor Design Center at Austin, Texas and formed an Advanced Media applications research activity. Weiser was appointed an Intel Fellow in 1996. In 2002 he became an IEEE Fellow and in 2005 an ACM Fellow, while in 2016 he was awarded the prestigious Eckert Mauchly award. Prior to his career at Intel, Professor Weiser worked for the Israeli Department of Defense as a research and system engineer and later with National Semiconductor Design Center in Israel, where he led the design of the NS32532 microprocessor.