Lecturer Bios

Per Stenström

Photo of Per StenströmPer Stenström is professor at Chalmers University of Technology. His research interests are in computer architecture. He has authored or co-authored four textbooks, more than 150 publications and ten patents in this area. He has coordinated several national and European projects and is a recipient of an ERC advanced grant. He has been program chairman of several top-tier IEEE conferences including IEEE/ACM Symposium on Computer Architecture and acts as Senior Associate Editor of ACM TACO, IEEE Micro Magazine and is Associate Editor-in-Chief of JPDC. He has a keen interest in teaching and has recently launched two MOOCs on computer design through ChalmersX (Chalmers’s MOOC offerings at the edX platform). He is also heavily involved in innovation initiatives and has founded two startup companies. He is a Fellow of the ACM and the IEEE and a member of Academia Europaea, the Royal Swedish Academy of Engineering Sciences and the Royal Spanish Academy of Engineering Science.

Uri Weiser

Photo of Uri WeiserUri Weiser is a Professor emeritus at the Electrical Engineering department, the Technion IIT and is in the advisory board of numerous startups. He received the bachelor and master degrees in EE from the Technion and Ph.D in CS from the University of Utah, Salt Lake City. Professor Weiser worked at Intel from 1988 till 2007. At Intel, Weiser initiated the definition of the Pentium® processor, drove the definition of Intel's MMX™ technology, invented the Trace Cache, co-managed the a new Intel Microprocessor Design Center at Austin, Texas and formed an Advanced Media applications research activity. Professor Weiser was appointed an Intel Fellow in 1996, in 2002 he became an IEEE Fellow and in 2005 an ACM Fellow. In 2016 Professor Weiser received the IEEE/ACM Eckert-Mauchly Award for “leadership, as well as pioneering industry and academic work in high performance processors and multimedia architectures”. The Eckert-Mauchly award is known as the computer architecture community’s most prestigious award. Prior to his career at Intel, Professor Weiser worked for the Israeli Department of Defense as a research and system engineer and later with National Semiconductor Design Center in Israel, where he led the design of the NS32532 microprocessor.

Luca Benini

Photo of Luca BeniniLuca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. He has been visiting professor at Stanford University, IMEC, EPFL. In 2009-2012 he served as chief architect in STmicroelectronics France. Dr. Benini's research interests are in energy-efficient computing systems design, from embedded to high-performance. He is also active in the design ultra-low power VLSI Circuits and smart sensing micro-systems.He has published more than 900 peer-reviewed papers and five books (h-index 95). Benini is an ERC-advanced grant winner, a Fellow of the ACM, of the IEEE and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award.

Mauro Olivieri

Photo of Mauro OlivieriMauro Olivieri received the Master (Laurea) degree in electronics engineering "cum laude" in 1991 and the Doctorate degree in electronics and computer engineering in 1994 from the University of Genoa, Italy, where he was assistant professor from 1995 to 1998. In 1998 he joined Sapienza University of Rome as associate professor, teaching Digital Electronics and Digital Integrated System Architectures. His research interests are digital system-on-chip design, microprocessor core design and digital nano-scale circuits. He was the scientific responsible for Sapienza University for 2 FP7 ENIAC JU European projects, 1 FP7 IAPP European project, 4 PRIN/FIRB national projects, 10 MIUR University Projects, and 7 research contracts with industrial commitment. He was a technical expert for the Italian Economic Development Ministry in the national “Smart Specialization Strategy” project on the topic “Smart Cities/Communities”. He is an evaluator for the European Commission in the ECSEL Joint Undertaking. He is a visiting researcher at the Barcelona Supercomputing Center within the European Processor Initiative project. He authored over 100 papers and a textbook in three volumes on digital VLSI design. He has been a member of the TPC of IEEE DATE and was General Co-Chair of IEEE/ACM ISLPED’15. He is a senior member of the IEEE.

Jesús Labarta

Photo of Jesús LabartaJesús Labarta is full professor on Computer Architecture at the Technical University of Catalonia (UPC) since 1990. Since 2005 he is responsible of the Computer Science Research Department within the Barcelona Supercomputing Center (BSC). His major directions of current work relate to performance analysis tools, programming models and resource management. His team distributes the Open Source BSC tools (Paraver and Dimemas) and performs research on increasing the intelligence embedded in the performance analysis tools. He is involved in the development of the OmpSs programming model and its different implementations for SMP, GPUs and cluster platforms.

David Carrera

Photo of David CarreraDavid Carrera received the MS degree at the Technical University of Catalonia (UPC) in 2002 and his PhD from the same university in 2008. He is an associate professor at the Computer Architecture Department of the UPC. He is also the Head of the "DataCentric Computing" research group at the Barcelona Supercomputing Center (BSC). His research interests are focused on the performance management of data center workloads. In 2018 he was awarded a medal in the Agustín de Betancourt prize for young researchers by the Spanish Royal Academy of Engineering. He is co-founder and Scientific Director of the start-up NearbyComputing SL. In 2015 he was awarded an ERC Starting Grant for the project HiEST (2015-2020), and ICREA Academia award (2015-2020) and an ERC Proof of Concept grant ('Hi-OMICS') in 2017 to explore the commercialization of an SDI orchestrator for genomics workloads. He has participated in several EU-funded projects and has led the team at BSC that has developed the Aloja project (aloja.bsc.es) and the servIoTicy platform (servioticy.com). He is the PI for several industrial projects and collaborations with IBM, Microsoft Intel and Cisco among others. He was a summer intern at IBM Watson (Hawthorne, NY) in 2006, and a Visiting Research Scholar at IBM Watson (Yorktown, NY) in 2012. He received an IBM Faculty Award in 2010. He is an IEEE and ACM member.

Silvio Micali

Photo of Silvio MicaliSilvio Micali has received his Laurea in Mathematics from the University of Rome, and his PhD in Computer Science from the University of California at Berkeley. Since 1983, he has been on the faculty of the Electrical Engineering and Computer Science Department at MIT. His research interests are cryptography, zero knowledge, pseudo-random generation, Byzantine agreement, secure protocols, mechanism design, and distributed ledgers. Silvio Micali is the recipient of the Turing Award (in computer science), the Gödel Prize (in theoretical computer science), and the RSA prize (in cryptography). He is a member of the National Academy of Sciences, the National Academy of Engineering, of the American Academy of Arts and Sciences, and of the Academia dei Lincei. Furthermore, he is the founder of Algorand LLC. Algorand is a new foundational blockchain, developed from scratch, on totally new principles, which simultaneously guarantees true decentralization, scalability, and security.

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Edge Computing

ACM Queue’s “Research for Practice” is your number one resource for keeping up with emerging developments in the world of theory and applying them to the challenges you face on a daily basis. RfP consistently serves up expert-curated guides to the best of CS research, and relates these breakthroughs to the challenges that software engineers face every day. In this installment of RfP is by Nitesh Mor, a PhD candidate at UC Berkeley working on the next generation of globally distributed computer systems with a special focus on data security and privacy. Titled “Edge Computing,” this RfP gives an overview of some of the most exciting work being done in the area of computing infrastructures and applications. It provides an academic view of edge computing through samples of existing research whose applications will be highly relevant in the coming years.